1. Field of the Invention
This application relates to the field of computer data storage and more particularly to the field of configuring a cache in a computer data storage system having multiple processors accessing the cache.
2. Description of Related Art
Host processor systems may store and retrieve data using a storage device containing a plurality of host interface units, disk drives, and disk interface units. Such storage devices are provided, for example, by EMC Corporation of Hopkington, Mass. and disclosed in U.S. Pat. No. 5,206,939 to Yanai et al., U.S. Pat. No. 5,778,394 to Galtzur et al., U.S. Pat. No. 5,845,147 to Vishlizzky et al., and U.S. Pat. No. 5,857,208 to Ofek. The host systems access the storage device through a plurality of channels provided therewith. Host systems provide data and access control information through the channels to the storage device and storage device provides data to the host systems also through the channels. The host systems do not address the disk drives of the storage device directly, but rather, access what appears to the host systems as a plurality of logical disk units. The logical disk units may or may nor correspond to the actual disk drives. Allowing multiple host systems to access the single storage device unit allows the host systems to share data stored therein.
Performance of a storage system may be improved by using a cache. In the case of a disk drive system, the cache may be implemented using a block of semiconductor memory that has a relatively lower data access time than the disk drive. Data that is accessed is advantageously moved from the disk drives to the cache so that the second and subsequent accesses to the data may be made to the cache rather than to the disk drives. Data that has not been accessed recently may be removed from the cache to make room for new data. Often such cache accesses are transparent to the host system requesting the data.
One technique for implementing a cache is to store the data in blocks and link each of the blocks together in a doubly linked ring list referred to herein as a “logical ring unit” (LRU). Each block of the LRU represents a block of data from a logical disk unit. The blocks are placed in the doubly linked ring list in the order in which they are retrieved from the disk. A pointer may point to the block that was most recently added to the list. Thus, when a new block is to be added to the cache, the structure of the LRU, in combination with the head pointer, may be used to determine the oldest block in the LRU that is to be removed to make room for the new block.
A drawback with the LRU mechanism is that only one process may access and manipulate the ring list at a time since the complexity of the doubly linked ring structure makes it difficult to allow more than one process to manipulate to the data structure at any time. One way to enforce this one-at-a-time access is to use a software lock, which is a conventional semaphore-like mechanism that allows a process exclusive access to the LRU. However, when multiple processors need to use the cache, then the exclusive LRU access policy may become a bottleneck. In addition, in some instances, it may be desirable to provide a mechanism for adjusting cache services provided to the host processor systems coupled to the storage device so that some of the host processors may receive better cache performance than other ones of the host processors.